ATmega16 8-Bit Timer Example
20. November 2011
This example shall demonstrate the usage of Timer Overflow Interrupts using the 8-bit timer Timer0 of an ATmega16.
We setup a prescale value of 1024 to divide the system clock appropriately. After doing this we set bit 0 (TOV0) of the Timer Interrupt Register and the bit 0 (TOIE0) of the Timer Mask Register to 1. Don't forget to enable interrupts (sei). Now our Interrupt Service Routine (ISR) will be called and performed if such an interrupt (overflow of Timer0) occurs.
With a system clock of 1MHz such an interrupt shall occur 3,83 times per second (about every 262.000 clocks).
.include "m16def.inc"
.LIST
.LISTMAC
.CSEG
rjmp start
.ORG OVF0addr ; jump after Timer0 overflow
rjmp ISR_TIMER0 ; to this ISR and perform it
.ORG $2A
start:
ldi r16, LOW(RAMEND) ; init Stack
out SPL, r16
ldi r16, HIGH(RAMEND)
out SPH, r16
ser r16
out DDRA, r16
ldi r16, 0
out PORTA, r16
ldi r16, (1 << CS02) | (1 << CS00)
out TCCR0, r16 ; setup prescale value 1024
ldi r16, 1 << TOV0 ; set Timer Overflow Flag
out TIFR, r16 ; to 1 (an overflow shall
ldi r16, 1 << TOIE0 ; trigger a Timer Overflow
out TIMSK, r16 ; Interrupt)
ser r16
out DDRB, r16
sei ; activate interrupts
loop:
nop
rjmp loop
ISR_TIMER0:
push r16 ; save current value of reg R16
in r16, SREG ; save current value of SREG
push r16 ;
in r16, PORTB ; read PortB
inc r16
out PORTB, r16 ; increment read value and write back
pop r16
out SREG, r16
pop r16
reti
.EXIT
We setup a prescale value of 1024 to divide the system clock appropriately. After doing this we set bit 0 (TOV0) of the Timer Interrupt Register and the bit 0 (TOIE0) of the Timer Mask Register to 1. Don't forget to enable interrupts (sei). Now our Interrupt Service Routine (ISR) will be called and performed if such an interrupt (overflow of Timer0) occurs.
With a system clock of 1MHz such an interrupt shall occur 3,83 times per second (about every 262.000 clocks).
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HILFE
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